Semiconductor memory typically includes redundant memory that is used to replace memory of a main memory array. Replacement, that is, mapping memory addresses of the memory to be replaced to redundant memory, most often occurs when some of the memory of the main memory array is defective. By replacing the defective memory with functional redundant memory, the memory can be salvaged rather than discarded.
The main memory array is divided into several sub-parts, for example, into banks of memory, which are further divided into memory sections of the main memory array. In many memory array architectures, a limited amount of redundant memory is provided for each of the memory sections, and can be used only to replace memory in the respective memory section. Unused redundant memory of a memory section cannot be used to replace memory of another memory section that is in need of more redundant memory. Consequently, if the number or arrangement of defective memory of a memory section is such that they cannot be repaired by the limited redundant memory dedicated to that memory section, the entire memory is discarded, or in some instances, downgraded to a memory having less overall capacity. Neither result is as desirable as fully repairing the memory.
FIG. 1 illustrates a portion of a main memory array 100. The main memory array 100 utilizes an “open-digit line” sense amplifier architecture. Open-digit line sense amplifier architectures, as known, have each digit line (of a pair of digit lines coupled to a respective sense-amplifier) extending into a different memory section of the array. FIG. 1 includes more detailed illustrations of two different groups 110, 120 of memory sections. Each group 110, 120 is shown in FIG. 1 as having a central memory section 132, a first adjacent memory section 134, and a second adjacent memory section 136. Additionally, each group 110, 120 includes a first set of sense-amplifiers 142 disposed between the central and first adjacent memory sections 132, 134 and a second set of sense-amplifiers 144 is disposed between the central and second adjacent memory sections 132, 136. Due to the open-digit line architecture, each sense-amplifier of the first set of sense-amplifiers is coupled to one digit line extending into the central memory section 132 and a second digit line extending into the first adjacent memory sections 134, and each sense-amplifier of the second set of sense-amplifiers is coupled to one digit line extending into the central memory section 132 and a second digit line extending into the second adjacent memory section 136.
In an open-digit line architecture, some failure modes result in a block of three adjacent memory sections failing. As previously discussed, each of the memory sections typically have limited redundant memory that can be used to repair several failures in the respective section. In order to minimize the extra area needed for the redundant memory, the amount of redundant memory per memory section is much less than would be needed to repair the entire memory section. If the failure requires more redundant memory than is available for the memory section, the memory section is considered un-repairable. In some instances, the inability to repair will result, as previously mentioned, in a block of three adjacent memory sections failing. For example, with reference to FIG. 1, where several of the digit lines of the central memory section 132, in particular, the digit lines coupled to sense-amplifiers of the first set of sense-amplifiers 142 and of the second set of sense-amplifiers 144, have short circuited to one another, the sense amplifiers of both the first and second sets of sense-amplifiers 142, 144 may be rendered inoperable. Consequently, not only is memory of the central memory section 132 defective but memory of the first and second adjacent memory sections may be defective as well, resulting in three adjacent memory sections failing. This type of catastrophic block failure will typically result in the entire memory device being considered inoperable.
Therefore, there is a need for a redundant memory architecture that can replace memory of entire memory sections and is sensitive to the desire to reduce the additional area used for redundant memory.